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MCP6G01/1R/1U/2/3/4
110 A Selectable Gain Amplifier
Features
* 3 Gain Selections: - +1, +10, +50 V/V * One Gain Select Input per Amplifier * Rail-to-Rail Input and Output * Low Gain Error: 1% (max.) * High Bandwidth: 250 kHz to 900 kHz (typ.) * Low Supply Current: 110 A (typ.) * Single Supply: 1.8V to 5.5V * Extended Temperature Range: -40C to +125C
Description
The Microchip Technology Inc. MCP6G01/1R/1U/2/3/4 are analog Selectable Gain Amplifiers (SGA). They can be configured for gains of +1 V/V, +10 V/V, and +50 V/V through the Gain Select input pin(s). The Chip Select pin on the MCP6G03 can put it into shutdown to conserve power. These SGAs are optimized for single supply applications requiring reasonable quiescent current and speed. The single amplifiers MCP6G01, MCP6G01R, MCP6G01U, and MCP6G03, are available in 5-pin SOT-23 package and the dual amplifier MCP6G02, are available in 8-pin SOIC and MSOP packages. The quad amplifier MCP6G04 is available in 14-pin SOIC and TSSOP packages. All parts are fully specified from -40C to +125C.
Typical Applications
* * * * * A/D Converter Driver Industrial Instrumentation Bar Code Readers Metering Digital Cameras
Package Types
MCP6G01 SOIC, MSOP
NC 1 8 NC 7 VDD 6 VOUT 5 NC GSEL 2 VIN 3 VSS 4
Block Diagram
VDD VIN Gain Switches Gain Select Logic 5 M CS (MCP6G03 only) VSS Gain (V/V) 1 10 50 Note: 0 VDD VSS is assumed to be 0V GSEL Voltage (Typ.) (V) VDD/2 (or open) Resistor Ladder (RLAD) RF VOUT 3
MCP6G03 SOIC, MSOP
NC 1 GSEL 2 VIN 3 VSS 4 8 CS 7 VDD 6 VOUT 5 NC
MCP6G01 SOT-23-5
VOUT 1 VSS 2 VIN 3
MCP6G02 SOIC, MSOP
5 VDD VOUTA 1 GSELA 2 4 GSEL VINA 3 VSS 4 8 VDD 7 VOUTB 6 GSELB 5 VINB
GSEL
RG
MCP6G01R SOT-23-5
VOUT 1 VDD 2 VIN 3 5 VSS
MCP6G04 SOIC, TSSOP
VOUTA 1 14 VOUTD 13 GSELD 12 VIND 11 VSS 10 VINC 9 GSELC 8 VOUTC
GSELA 2 4 GSEL VINA 3 VDD 4 VINB 5 VOUTB 7 4 VOUT
MCP6G01U SOT-23-5
VIN 1 VSS 2 GSEL 3
5 VDD GSELB 6
(c) 2006 Microchip Technology Inc.
DS22004B-page 1
MCP6G01/1R/1U/2/3/4
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See Section 4.1.4 "Input Voltage and Current Limits".
Absolute Maximum Ratings
VDD - VSS ........................................................................7.0V Current at Analog Input Pin (VIN) ......................................2 mA Analog Input (VIN) ..................... VSS - 1.0V to VDD + 1.0V All other Inputs and Outputs........... VSS - 0.3V to VDD + 0.3V Output Short Circuit Current...................................continuous Current at Output and Supply Pins ................................ 30 mA Storage Temperature.....................................-65C to +150C Junction Temperature.................................................. +150C ESD protection on all pins (HBM; MM) ................ 4 kV; 200V
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, GSEL = VDD/2, and CS is tied low.
Parameters
Amplifier Inputs (VIN) Input Offset Voltage Input Offset Voltage Drift Power Supply Rejection Ratio Input Bias Current Input Bias Current at Temperature Input Impedance Amplifier Gain Nominal Gains DC Gain Error G = +1 G +10 DC Gain Drift G = +1 G +10 Ladder Resistance (Note 1) Ladder Resistance Ladder Resistance across Temperature Amplifier Output DC Output Non-linearity G = +1
Sym
VOS VOS/TA PSRR IB IB IB ZIN G gE gE G/TA G/TA RLAD RLAD/TA
Min
-4.5 -- -- 65 -- -- -- -- -- -0.3 -1.0 -- -- 200 --
Typ
1.0 1.0 2 80 1 30 1000 1013||6 1 to 50 -- -- 1 4 350 -1800
Max
+4.5 -- -- -- -- -- 5000 -- -- +0.3 +1.0 -- -- 500 --
Units
mV mV V/C dB pA pA pA ||pF V/V % % ppm/C ppm/C k ppm/C G = +1
Conditions
G = +10, +50 G = +1, TA = -40C to +125C G = +1 (Note 1) TA = +85C TA = +125C
+1, +10 or +50 VOUT 0.3V to VDD - 0.3V VOUT 0.3V to VDD - 0.3V TA = -40C to +125C TA = -40C to +125C
TA = -40C to +125C
VONL VONL
-0.2 -0.1 -0.05 VSS+10 VSS+10 -- --
-- -- -- -- -- 7 20
+0.2 +0.1 +0.05 VDD-10 VDD-10 -- --
% of FSR VOUT = 0.3V to VDD - 0.3V, VDD = 1.8V % of FSR VOUT = 0.3V to VDD - 0.3V, VDD = 5.5V % of FSR VOUT = 0.3V to VDD - 0.3V mV mV mA mA G = +1; 0.3V output overdrive G +10; 0.5V output overdrive VDD = 1.8V VDD = 5.5V
DC Output Non-linearity, G = +10, +50 Maximum Output Voltage Swing Short Circuit Current Note 1:
VONL VOH, VOL VOH, VOL ISC ISC
2:
RLAD (RF+RG in Figure 4-1) connects VSS, VOUT, and the inverting input of the internal amplifier. Thus, VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is recommended that the VSS pin be tied directly to ground to avoid noise problems. IQ includes current in RLAD (typically 0.6 A at VOUT = 0.3V), and excludes digital switching currents.
DS22004B-page 2
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, GSEL = VDD/2, and CS is tied low.
Parameters
Power Supply Supply Voltage Quiescent Current per Amplifier Note 1:
Sym
VDD IQ
Min
1.8 60
Typ
-- 110
Max
5.5 170
Units
V A
Conditions
IO = 0 (Note 2)
2:
RLAD (RF+RG in Figure 4-1) connects VSS, VOUT, and the inverting input of the internal amplifier. Thus, VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is recommended that the VSS pin be tied directly to ground to avoid noise problems. IQ includes current in RLAD (typically 0.6 A at VOUT = 0.3V), and excludes digital switching currents.
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters
Frequency Response -3dB Bandwidth
Sym
BW BW BW
Min
-- -- -- -- -- -- -- -- --
Typ
900 350 250 0.3 0 0.7 0.0029 0.18 1.3
Max
-- -- -- -- -- -- -- -- --
Units
kHz kHz kHz dB dB dB % % %
Conditions
G = +1, VOUT < 100 mVP-P (Note 1) G = +10, VOUT < 100 mVP-P (Note 1) G = +50, VOUT < 100 mVP-P (Note 1) G = +1; VOUT < 100 mVP-P G = +10, VOUT < 100 mVP-P G = +50; VOUT < 100 mVP-P VOUT = 1.75V 1.4VPK, VDD = 5.0V, BW = 80 kHz VOUT = 2.5V 1.4VPK, VDD = 5.0V, BW = 80 kHz VOUT = 2.5V 1.4VPK, VDD = 5.0V, BW = 80 kHz G=1 G = 10 G = 50 f = 0.1 Hz to 10 Hz (Note 2) f = 0.1 Hz to 30 kHz (Note 2)
Gain Peaking
GPK GPK GPK
Total Harmonic Distortion plus Noise f = 1 kHz, G = +1 V/V f = 1 kHz, G = +10 V/V f = 1 kHz, G = +50 V/V Step Response Slew Rate SR SR SR Noise Input Noise Voltage Input Noise Voltage Density Eni Eni eni eni eni Input Noise Current Density Note 1: 2: ini -- -- -- -- -- -- 9 50 38 46 41 4 -- -- -- -- -- -- VP-P VP-P -- -- -- 0.50 2.3 4.5 -- -- -- V/s V/s V/s THD+N THD+N THD+N
nV/Hz G = +1 V/V, f = 10 kHz (Note 2) nV/Hz G = +10 V/V, f = 10 kHz (Note 2) nV/Hz G = +50 V/V, f = 10 kHz (Note 2) fA/Hz f = 10 kHz
See Table 4-1 for a list of typical numbers and Figure 2-31 for the frequency response versus gain. Eni and eni include ladder resistance thermal noise.
(c) 2006 Microchip Technology Inc.
DS22004B-page 3
MCP6G01/1R/1U/2/3/4
DIGITAL ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = 25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters
CS Low Specifications CS Logic Threshold, Low CS Input Current, Low CS High Specifications CS Logic Threshold, High CS Input Current, High Quiescent Current per Amplifier, Shutdown Mode (IDD) Quiescent Current per Amplifier, Shutdown Mode (ISS) (Note 3) CS Dynamic Specifications Input Capacitance Input Rise/Fall Times CS Low to Amplifier Output High Turn-on Time
Sym
VCSL ICSL VCSH ICSH IDD_SHDN ISS_SHDN ISS_SHDN CCS tCSRF tCSON tCSON
Min
0 -- 0.8VDD -- -- -- -- -- -- -- -- -- -- -- 0.15VDD 0.65VDD -10 +1.5 -- -- -- -- -- -- -- --
Typ
-- 30 -- 0.8 120 -2.4 -7.2 10 -- 40 7 30 0.40 0.55 -- -- -- -- 8 -- 45 95 10 12 9 8
Max
0.2VDD -- VDD -- -- -- -- -- 2 -- -- -- -- -- 0.35VDD 0.85VDD -1.5 +10 -- 10 -- -- -- -- -- --
Units
V pA V A pA A A pF s s s s V V V V A A pF s mV mV s s s s (Note 2) VDD = 1.8V VDD = 5.5V (Note 2) CS = 0V CS = 0V CS = VDD
Conditions
CS = VDD = 5.5V CS = VDD, MCP6G03 CS = VDD = 1.8V, MCP6G03 CS = VDD = 5.5V, MCP6G03
G = +1 V/V, VDD = 1.8V, VIN = 0.9VDD CS = 0.2VDD to VOUT = 0.8VDD G = +1 V/V, VDD = 5.5V, VIN = 0.9VDD CS = 0.2VDD to VOUT = 0.8VDD G = +1 V/V, VIN = VDD/2, CS = 0.8VDD to VOUT = 0.1VDD/2 VDD = 1.8V VDD = 5.5V Gain changes between 1 and 10, IGSEL = 0 Gain changes between 1 and 50, IGSEL = 0 GSEL voltage = 0.3VDD GSEL voltage = 0.7VDD
CS High to Amplifier Output High-Z Turn-off Time Hysteresis GSEL Specifications (Note 1) GSEL Logic Threshold, Low GSEL Logic Threshold, High GSEL Input Current, Low GSEL Input Current, High Input Capacitance Input Rise/Fall Times Hysteresis GSEL Low to Valid Output Time, G = +1 to +10 Select GSEL Middle to Valid Output Time, G = +10 to +1 Select GSEL High to Valid Output Time, G = +1 to +50 Select GSEL Middle to Valid Output Time, G = +50 to +1 Select Note 1: 2: 3:
tCSOFF VCSHY VCSHY VGSL VGSH IGSL IGSH CGSEL tGSRF VGSHY VGSHY tGSL1 tGSM10 tGSH1 tGSM50
GSEL Dynamic Specifications (Note 1)
VIN = 150 mV, GSEL = 0.25VDD to VOUT = 1.37V VIN = 150 mV, GSEL = 0.25VDD to VOUT = 0.28V VIN = 30 mV, GSEL = 0.75VDD to VOUT = 1.35V VIN = 30 mV, GSEL = 0.75VDD to VOUT = 0.18V
GSEL is a tri-level input pin. The gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high. Not tested in production. Set by design and characterization. ISS_SHDN includes the current through the CS pin, RL and RLAD, and excludes digital switching currents. The block diagram on the from page shows these current paths (through VSS).
DS22004B-page 4
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
DIGITAL ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = 25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters
GSEL High to Valid Output Time, G = +10 to +50 Select GSEL Low to Valid Output Time, G = +50 to +10 Select Note 1: 2: 3:
Sym
tGSH10 tGSL50
Min
-- --
Typ
12 9
Max
-- --
Units
s s
Conditions
VIN = 30 mV, GSEL = 0.75VDD to VOUT = 1.38V VIN = 30 mV, GSEL = 0.25VDD to VOUT = 0.42V
GSEL is a tri-level input pin. The gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high. Not tested in production. Set by design and characterization. ISS_SHDN includes the current through the CS pin, RL and RLAD, and excludes digital switching currents. The block diagram on the from page shows these current paths (through VSS).
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.8V to +5.5V, and VSS = GND.
Parameters
Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SOT-23 Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note 1:
Sym
TA TA TA JA JA JA JA JA
Min
-40 -40 -65 -- -- -- -- --
Typ
-- -- -- 256 163 206 120 100
Max
+125 +125 +150 -- -- -- -- --
Units
C C C C/W C/W C/W C/W C/W
Conditions
(Note 1)
The MCP6G01/1R/1U/2/3/4 family of SGAs operates over this temperature range, but operation must not cause TJ to exceed Maximum Junction Temperature (+150C).
VIN
0.150V
0.030V
GSEL tGSL1 1.50V VOUT 0.15V 0.15V 0.03V tGSM10 tGSH1 1.50V 0.30V 0.03V tGSM50 tGSH10 tGSL50
1.50V 0.30V
FIGURE 1-1:
Gain Select Timing Diagram.
(c) 2006 Microchip Technology Inc.
DS22004B-page 5
MCP6G01/1R/1U/2/3/4
CS tCSON tCSOFF
VOUT IDD
High-Z
0.9VDD
High-Z
110 A (typ.) 120 pA (typ.) -VDD / 7 M (typ.)
ISS
-110 A (typ.)
ICS
VDD / 7 M (typ.)
30 pA (typ.)
FIGURE 1-2:
SGA Chip Select Timing Diagram.
DS22004B-page 6
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
1.1
1.1.1
DC Output Voltage Specs / Model
IDEAL MODEL
The DC Gain Drift (G/TA) can be calculated from the change in gE across temperature. This is shown in the following equation:
The ideal SGA output voltage (VOUT) is (see Figure 1-3):
EQUATION 1-4:
g E G T A = G --------- , T A g E G T A = 100% --------- , T A in units of V/V/C
EQUATION 1-1:
V O_ID = GV IN Where: G is the nominal gain V REF = V SS = 0V This equation holds when there are no gain or offset errors.
in units of %/C
VOUT (V) VDD VDD-0.3
V
T OU IN _L D _I VO
1.1.2
LINEAR MODEL
V2
VO
The SGA's linear region of operation is modeled by the line VO_LIN shown in Figure 1-3. VO_LIN includes offset and gain errors, but does not include non-linear effects.
EQUATION 1-2:
V O_LIN = G ( 1 + g E ) V IN - 0.3V + V OS + 0.3V ---------- G Where: G is the nominal gain gE is the gain error VOS is the input offset voltage V REF = V SS = 0V This line's endpoints are 0.3V from the supply rails (VO_ID = 0.3V and VDD - 0.3V). The gain error and input offset voltage specifications (in the electrical specifications) relate to Figure 1-3 as follows:
V1 0.3 0 0 0.3 G VDD-0.3 VDD G G VIN (V)
FIGURE 1-3: 1.1.3
Output Voltage Model.
OUTPUT NON-LINEARITY
Figure 1-4 shows the Integral Non-Linearity (INL) of the output voltage. INL is the output non-linearity error not explained by VO_LIN:
EQUATION 1-5:
INL = V OUT - V O_LIN The output non-linearity specification (in the Electrical Specifications, with units of % of FSR) is related to Figure 1-4 by:
EQUATION 1-3:
V2 - V1 g E = 100% ---------------------------V DD - 0.6V V1 V OS = ------------------------ , G ( 1 + gE ) Where: V 1 = V OUT - V O_ID , V 2 = V OUT - V O_ID , V O_ID = 0.3V V O_ID = V DD - 0.3V G = +1
EQUATION 1-6:
max ( V 3, V 4 ) V ONL = 100% -----------------------------V DD - 0.6V Where: V 3 = max ( - INL ) V 4 = max ( INL ) Note that the Full Scale Range (FSR) is VDD - 0.6V (0.3V to VDD - 0.3V).
The input offset specification describes VOS at G = +1 V/V.
(c) 2006 Microchip Technology Inc.
DS22004B-page 7
MCP6G01/1R/1U/2/3/4
INL (V) V4 0 V3 0.3 G VDD-0.3 VDD G G VIN (V)
0
FIGURE 1-4:
Output Voltage INL.
DS22004B-page 8
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Percentage of Occurrences 30% 25% 20% 15% 10% 5% 0% -0.28 -0.24 -0.20 -0.16 -0.12 -0.08 -0.04 0.00 0.04 0.08 0.12 0.16 0.20 0.24 0.28
Percentage of Occurrences
2460 Samples G = +1
18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
2459 Samples G = +1 TA = -40 to +125C
0
1
2
3
4 12 10
-5
-4
-3
-2
DC Gain Error (%)
DC Gain Drift (ppm/C)
FIGURE 2-1:
14% 12% 10% 8% 6% 4% 2% 0% -0.7 -0.6 -0.5 -0.4
DC Gain Error, G = +1.
FIGURE 2-4:
14% 12% 10% 8% 6% 4% 2% 0%
DC Gain Drift, G = +1.
Percentage of Occurrences
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Percentage of Occurrences
4916 Samples G +10
-1
4912 Samples G +10 TA = -40 to +125C
0
2
4
6
-8
-6
-4
-2
8
10 8
-14
-12
-10
DC Gain Error (%)
DC Gain Drift (ppm/C)
FIGURE 2-2:
20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
DC Gain Error, G +10.
FIGURE 2-5:
22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
DC Gain Drift, G +10.
Percentage of Occurrences
G = +50 G = +10 G = +1
0.5
1.5
2.5
3.5
-4.5
-3.5
-2.5
-1.5
-0.5
4.5
Percentage of Occurrences
2460 Samples
1612 Samples G = +1, +10, +50 TA = -40 to +125C
0
2
4
-8
-6
-4
-2
6
-12
Input Offset Voltage (mV)
-10
Input Offset Voltage Drift (V/C)
FIGURE 2-3:
Input Offset Voltage.
FIGURE 2-6:
Input Offset Voltage Drift.
(c) 2006 Microchip Technology Inc.
DS22004B-page 9
12
14
5
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
6 Input, Output Voltage (V) 5 4 3 2 1 0 -10.0E+00
1.0E-03 2.0E-03 3.0E-03 4.0E-03 5.0E-03 6.0E-03 7.0E-03 8.0E-03 9.0E-03 1.0E-02
VOUT
Crosstalk, Input Referred (dB)
VIN
VDD = 5.0V G = +1 V/V
Time (1 ms/div)
0 -10 RS = 1 M -20 R = 100 k S -30 RS = 10 k -40 -50 -60 -70 -80 -90 -100 -110 -120 1k 1.E+03
VDD = 5.0V G = 50 V/V
RS = 0
10k 1.E+04 Frequency (Hz)
100k 1.E+05
FIGURE 2-7: The MCP6G01/1R/1U/2/3/4 family shows no phase reversal under overdrive.
120 110 PSRR (dB) 100 90 80 70 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
FIGURE 2-10: Crosstalk vs. Frequency, with G = 50 (circuit in Figure 4-7).
90 80 70 60 50 40 30 20 100 100 VDD = 1.8V G=1 1k 10k 1000 10000 Frequency (Hz) 100k 100000 G = 10
Power Supply Rejection Ratio (dB)
Input Referred
VDD = 5.5V G = 50
FIGURE 2-8:
10000 Input Noise Voltage Density (nV/ Hz)
PSRR vs. Temperature.
FIGURE 2-11:
160 Quiescent Current (mA) 140 120 100 80 60 40 20 0
PSRR vs. Frequency.
TA = +125C TA = +85C
1000
G = +1 = +10 = +50
100
TA = +25C TA = -40C
10 0.1 0.1
1 1
10 100 1k 10k 100k 10 100 1000 10000 10000 Frequency (Hz) 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V)
FIGURE 2-9: vs. Frequency.
Input Noise Voltage Density
FIGURE 2-12: Supply Voltage.
Quiescent Current vs.
DS22004B-page 10
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
0 Quiescent Current in Shutdown (A) -1 -2 -3 -4 -5 -6 -7 -8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) ISS_SHDN 0 -1 Quiescent Current in Shutdown (A) -2 -3 -4 -5 -6 -7 -8 -9 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 VDD = 5.5V
In Shutdown Mode VIN = VDD/2 CS = VDD
In Shutdown Mode VIN = VDD/2 VDD = 1.8V
FIGURE 2-13: Quiescent Current (ISS) in Shutdown Mode vs. Supply Voltage.
1,000 Input Bias Current (pA)
FIGURE 2-16: Quiescent Current (ISS) in Shutdown Mode vs. Temperature.
1.E-02 10m 1.E-03 1m 1.E-04 100 10 1.E-05 1 1.E-06 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12
100
10
Input Current Magnitude (A)
VDD = 5.5V VIN = VDD
1 55 65 75 85 95 105 115 125 Ambient Temperature (C)
+125C +85C +25C -40C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V)
FIGURE 2-14: Temperature.
10,000 Input Bias Current (pA) 1,000 100 10 1
Input Bias Current vs.
FIGURE 2-17: Voltage.
30 25 20 15 10 5 0
Input Bias Current vs. Input
Output Short Circuit Current Magnitude (mA)
VDD = 5.5V TA = +125C
TA = -40C TA = +25C TA = +85C TA = +125C
TA = +85C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V)
FIGURE 2-15: Voltage.
Input Bias Current vs. Input
FIGURE 2-18: Output Short Circuit Current vs. Supply Voltage.
(c) 2006 Microchip Technology Inc.
DS22004B-page 11
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
3 2 1 0 -1 -2 -3 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Ideal Output Voltage; GVIN (V) 1.8 G = +1 G = +10 G = +50 3 2 1 0 -1 -2 -3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ideal Output Voltage; GVIN (V) G = +10 G = +50 G = +1
Output Error, Input Referred; VOUT /G - V IN (mV)
Output Error, Input Referred; VOUT /G - V IN (mV)
VDD = +1.8V Representative Part
VDD = +5.5V Representative Part
FIGURE 2-19: Output Voltage Error vs. Ideal Output Voltage, with VDD = 1.8V.
Output Voltage Headroom; VDD - V OH and V OL - V SS (mV) 1000
FIGURE 2-22: Output Voltage Error vs. Ideal Output Voltage, with VDD = 5.5V.
4.0 Output Voltage Headroom; VDD-V OH and V OL-V SS (mV) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -50 -25 0 25 50 75 100 125 Ambient Temperature (C)
VDD = 1.8V: VOL-VSS VDD-VOH VDD = 5.5V: VDD-VOH VOL-VSS
100
VDD = +1.8V VDD - VOH
10
VDD = +5.5V VOL - VSS
1 0.01
0.1 1 Output Current Magnitude (mA)
10
FIGURE 2-20: Output Voltage Headroom vs. Output plus Ladder Current (circuit in Figure 4-4).
100k 1.E+05
FIGURE 2-23: vs. Temperature.
Output Voltage Headroom
Output Impedance Magnitude ()
Percentage of Occurrences
G = 50 = 10 =1
14% 12% 10% 8% 6% 4% 2% 0% -2000 -1900 -1800
1228 Samples TA = -40 to +125C
10k 1.E+04
1k 1.E+03
-1700
-1600
100 1.E+02 10k 1.E+04
100k 1M 1.E+05 1.E+06 Frequency (Hz)
10M 1.E+07
Ladder Resistance Drift (ppm/C)
FIGURE 2-21: Frequency.
Output Impedance vs.
FIGURE 2-24:
Ladder Resistance Drift.
DS22004B-page 12
(c) 2006 Microchip Technology Inc.
-1500
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
0.7 0.6 Slew Rate (V/s) 0.5 0.4 0.3 0.2 0.1 0.0 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 Rising Edge VDD = 1.8V 10 VDD = 5.5V VDD = 1.8V
VDD = 5.5V
Falling Edge
Output Voltage Swing (V
P-P )
G = +1 V/V
1
G = +1 G = +10 G = +50 0.1 1.E+03 1k 10k
1.E+04
100k
1.E+05
1.E+06
1M
Frequency (Hz)
FIGURE 2-25: with G = +1.
3.0 2.5 Slew Rate (V/s) 2.0 1.5 1.0 0.5 0.0 -50 -25
Slew Rate vs. Temperature,
FIGURE 2-28: Frequency.
4.0
Output Voltage Swing vs.
G = +10 V/V VDD = 5.5V Slew Rate (V/s) Falling Edge
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
G = +50 V/V VDD = 5.5V Falling Edge
Rising Edge
Rising Edge
0 25 50 75 Ambient Temperature (C)
100
125
-50
-25
0 25 50 75 Ambient Temperature (C)
100
125
FIGURE 2-26: with G = +10.
1M 1.E+06
Slew Rate vs. Temperature,
FIGURE 2-29: with G = +50.
1.E+06 1M
Slew Rate vs. Temperature,
Bandwidth (Hz)
Bandwidth (Hz)
G = +1 G = +10 G = +50
G = +1
G = +10 G = +50
100k 1.E+05
10k 1.E+04 100 1.E+02
10k 1k 1.E+03 1.E+04 Resistive Load ( )
100k 1.E+05
100k 1.E+05 10
100 Capacitive Load (pF)
1000
FIGURE 2-27: Load.
Bandwidth vs. Resistive
FIGURE 2-30: Load.
Bandwidth vs. Capacitive
(c) 2006 Microchip Technology Inc.
DS22004B-page 13
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
40 30 20 Gain (dB) 10 0 -10 -20 -30 -40 10k 1.E+04 100k 1M 1.E+05 1.E+06 Frequency (Hz) 10M 1.E+07 G = +50 Gain Peaking (dB) G = +10 G = +1 7 6 5 4 3 2 1 0 10 100 Capacitive Load (pF) 1000 G = +1 G = +10 G = +50
FIGURE 2-31:
Gain vs. Frequency.
FIGURE 2-34: Load.
1 Normalized Input Voltage, Output Voltage (V) 1 Normalized Input Voltage (100 mV/div) 1 1 1 0 0 0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
Gain Peaking vs. Capacitive
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VDD = +5.0V
VDD = +5.0V
Output Voltage (20 mV/div)
GVI VOUT G = +1 G = +10 G = +50
VOUT G = +50 G = +10 G = +1 GVIN
0.00 5.00 10.00 15.00
Time (5 s/div)
20.00
25.00
30.00
35.00
40.00
45.00
50.00
0.00
5.00
10.00
15.00
Time (5 s/div)
20.00
25.00
30.00
35.00
40.00
45.00
50.00
FIGURE 2-32: Response.
10 G = +50 THD + Noise (%) G = +10 0.1 0.01 G = +1 0.001 100 1.E+02 1
Small Signal Pulse
FIGURE 2-35: Response.
10 1 0.1 G = +1 0.01 0.001 100 1.E+02 G = +50 G = +10
Large Signal Pulse
VOUT = 2.8VP-P VDD = 5.0V Measurement BW = 80 kHz 1k 10k 1.E+03 1.E+04 Frequency (Hz) 100k 1.E+05
THD + Noise (%)
VOUT = 4 VP-P VDD = 5.0V Measurement BW = 80 kHz 1k 10k 1.E+03 1.E+04 Frequency (Hz) 100k 1.E+05
FIGURE 2-33: THD plus Noise vs. Frequency, VOUT = 2.8 VP-P.
FIGURE 2-36: THD plus Noise vs. Frequency, VOUT = 4.0 VP-P.
DS22004B-page 14
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
10 1 0.1 G = +1 0.01 0.001 VOUT = 0.8VDD f = 1 kHz Measurement BW = 80 kHz 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Power Supply Voltage (V) 5.0 5.5 G = +50 G = +10 THD + Noise (%) 1 0.1 G = +1 0.01 f = 1 kHz VDD = 5.0V Measurement BW = 80 kHz 10k 100k 1.E+04 1.E+05 Load Resistance () 1M 1.E+06 10 G = +50 G = +10
THD + Noise (%)
0.001 1k 1.E+03
FIGURE 2-37: Voltage.
10
THD plus Noise vs. Supply
FIGURE 2-40: Resistance.
5.0
THD plus Noise vs. Load
G = +50 THD + Noise (%) Output Voltage (V) 1 G = +10 0.1 G = +1 0.01 0.001 1 Output Swing (VP-P) 10 VDD = 5.0V f = 1 kHz Measurement BW = 80 kHz
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
0
GSEL VDD = 5.0V VIN = 0.030V VOUT (G = +50) (G = +1)
10 20 30
5 5 0 0 -5
-10 -15 -20 -25 -30 (G = +1) -35
100
Time (10 s/div)
40
50
60
70
80
90
-40
FIGURE 2-38: Swing.
5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
0 10 20 30
THD plus Noise vs. Output
FIGURE 2-41: Gain = 1 and 50.
5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
0
Gain Select Timing, with
Gain Select Voltage (V)
10 5 5 0 0 -5
GSEL VDD = 5.0V VIN = 0.030V VOUT (G = +50) (G = +10)
10 20 30 40 50
GSEL VDD = 5.0V VIN = 0.15V (G = +10) (G = +10)
5 5 0 0 -5
-10 -15 -20 -25 -30
-10 -15 -20 -25 -30 -35
80 90 100
VOUT (G = +1) Time (10 s/div)
40 50 60 70
-35
80 90 100
-40
(G = +10) Time (10 s/div)
60 70
-40
FIGURE 2-39: Gain = 1 and 10.
Gain Select Timing, with
FIGURE 2-42: Gain = 1 and 10.
Gain Select Timing, with
(c) 2006 Microchip Technology Inc.
DS22004B-page 15
Gain Select Voltage (V)
10
Gain Select Voltage (V)
10
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 VOUT is "ON" VDD = 1.8V VIN = 0.9VDD Chip Select Voltage (V) Output Voltage (mV) Shutdown G=1 G = 10 G = 50 CS Time (20 s/div) 1.8 0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 VOUT is "ON" VDD = 5.0V VIN = 0.9VDD Shutdown G=1 G = 10 G = 50 CS Time (20 s/div) 5 0 Chip Select Voltage (V) 7.0
Output Voltage (mV)
FIGURE 2-43: Output Voltage vs. Chip Select, with VDD = 1.8V.
10 8 6 4 2 0 -2 -4 -6 -8 -10
FIGURE 2-46: Output Voltage vs. Chip Select, with VDD = 5.0V.
10 8 6 4 2 0 -2 -4 -6 -8 -10
VDD = 1.8V
VDD = 5.5V
GSEL Current (A)
TA = +25C = +85C = +125C
GSEL Current (A)
TA = +125C = +85C = +25C
TA = +25C = +85C = +125C
TA = +125C = +85C = +25C
0.0
0.2
0.4
0.6 0.8 1.0 1.2 GSEL Voltage (V)
1.4
1.6
1.8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 GSEL Voltage (V)
FIGURE 2-44: GSEL Pin Current vs. GSEL Voltage, with VDD = 1.8V.
22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Percentage of Occurrences 1228 Samples GSEL = 0.3VDD VDD = 5.5V VDD = 1.8V
FIGURE 2-47: GSEL Pin Current vs. GSEL Voltage, with VDD = 5.5V.
20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Percentage of Occurrences 1228 Samples GSEL = 0.7VDD
VDD = 1.8V
VDD = 5.5V
-7.0
-6.6
-6.2
-5.8
-5.4
-5.0
-4.6
-4.2
-3.8
-3.4
-3.0
3.0
3.4
3.8
4.2
4.6
5.0
5.4
5.8
6.2
GSEL Current (A)
GSEL Current (A)
FIGURE 2-45: GSEL Current, with GSEL Voltage of 0.3VDD.
FIGURE 2-48: GSEL Current, with GSEL Voltage of 0.7VDD.
DS22004B-page 16
(c) 2006 Microchip Technology Inc.
6.6
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL = 100 k to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% Percentage of Occurrences Percentage of Occurrences
1227 Samples G = +1 to +10
1228 Samples G = +1 to +50
VDD = 5.5V
VDD = 1.8V
VDD = 1.8V
VDD = 5.5V
0.213
0.218
0.222
0.227
0.231
0.236
0.241
0.245
0.250
0.255
0.259
0.736
0.741
0.745
0.750
0.755
0.759
0.764
0.768
Normalized GSEL Trip Point; VGSEL/VDD
Normalized GSEL Trip Point; VGSEL/VDD
FIGURE 2-49: GSEL Trip Point between G = +1 and G = +10.
FIGURE 2-50: GSEL Trip Point between G = +1 and G = +50.
(c) 2006 Microchip Technology Inc.
DS22004B-page 17
0.773
MCP6G01/1R/1U/2/3/4
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
MCP6G01 (SOIC, MSOP) 6 2 3 7 4 -- 1,5,8
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6G01 (SOT-23-5) 1 4 3 5 2 -- -- MCP6G01R (SOT-23-5) 1 4 3 2 5 -- -- MCP6G01U (SOT-23-5) 4 3 1 5 2 -- -- MCP6G03 6 2 3 7 4 8 1,5 Symbol VOUT GSEL VIN VDD VSS CS NC Description Analog Output Gain Select Input Analog Input Positive Power Supply Negative Power Supply Chip Select No Internal Connection
TABLE 3-2:
MCP6G02 1 2 3 8 5 6 7 -- -- -- 4 -- -- --
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6G04 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol VOUTA GSELA VINA VDD VINB GSELB VOUTB VOUTC GSELC VINC VSS VIND GSELD VOUTD Analog Output A Gain Select Input (SGA A) Analog Input A Positive Power Supply Analog Input B Gain Select Input (SGA B) Analog Output B Analog Output C Gain Select Input (SGA C) Analog Input C Negative Power Supply Analog Input D Gain Select Input (SGA D) Analog Output D Description
3.1
Analog Output
The output pin (VOUT) is a low impedance voltage source. The selected gain (G) and input voltage (VIN) determine its value.
3.2
Analog Input
The analog inputs (VIN) are high impedance CMOS inputs with low bias currents. Only three fixed, noninverting gains are available through these inputs.
Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground, and VDD is connected to the supply. VDD will need a local bypass capacitor (typically 0.01 F to 0.1 F) within 2 mm of the VDD pin. These parts need to use a bulk capacitor (typically 1.0 F to 10 F) within 100 mm of the VDD pin; it can be shared with nearby analog parts.
3.4
Digital Inputs
3.3
Power Supply (VSS and VDD)
The Chip Select (CS) input is a Schmitt-triggered, CMOS logic input. The Gain Select (GSEL) inputs are tri-level digital inputs. They function similar to normal logic inputs at low (G = +10) and high voltages (G = +50). The pin can also be set to mid-supply (G = +1) by a low impedance source, or by leaving this pin open.
The Positive Power Supply Pin (VDD) is 1.8V to 5.5V higher than the Negative Power Supply Pin (VSS). For normal operation, the other pins are at voltages between VSS and VDD.
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MCP6G01/1R/1U/2/3/4
4.0 APPLICATIONS INFORMATION
TABLE 4-1:
The MCP6G01/1R/1U/2/3/4 family of Selectable Gain Amplifiers (SGA) is based on simple analog building blocks (see Figure 4-1). Each of these blocks will be explained in more detail in the following subsections. VDD VIN Gain Switches Gain Select Logic 5 M CS (MCP6G03 only) VSS Gain (V/V) 1 10 50 Note: 0 VDD VSS is assumed to be 0V GSEL Voltage (Typ.) (V) VDD/2 (or open) Resistor Ladder (RLAD) RF VOUT 3
GAIN VS. INTERNAL COMPENSATION CAPACITOR
FPBW (kHz) Typ. 29 133 260 BW (kHz) Typ. 900 350 250
Gain (V/V) 1 10 50
Internal G x BW SR Comp. (MHz) (V/s) Cap. Typ. Typ. Large Medium Small 0.90 3.5 12.5 0.50 2.3 4.5
Note 1: 2: 3: 4:
GSEL
RG
Changing the compensation capacitor does not change the DC performance (e.g., VOS). G x BW is approximately the Gain Bandwidth Product of the internal op amp. FPBW is the Full Power Bandwidth at VDD = 5.5V, which is based on slew rate (SR). BW is the closed-loop, small signal -3 dB bandwidth.
4.1.2
RAIL-TO-RAIL INPUTS
The input stage of the internal op amp uses two differential input stages in parallel; one operates at low VIN (input voltage), while the other operates at high VIN. With this topology, the internal inputs can operate to 0.3V past either supply rail, although the output will clip the signal before that happens. The inputs need to be kept within a smaller range to prevent output clipping. The input offset voltage also reduces the range; most designs will need the following for normal operation:
FIGURE 4-1:
SGA Block Diagram.
EQUATION 4-1:
V OL V OH --------- + V OS < V IN < ---------- - V OS G G The transition between the two input stage occurs when VIN VDD - 1.1V (see Figure 2-19 and Figure 222). For the best distortion and gain linearity, avoid this region of operation.
4.1
Internal Op Amp
The internal op amp gives the right combination of bandwidth, accuracy, and flexibility.
4.1.1
COMPENSATION CAPACITORS
The internal op amp has three compensation capacitors (comp. caps.) connected to a switching network. They are selected to give good small signal bandwidth at high gains, and good slew rate (full power bandwidth) at low gains. The change in bandwidth as gain changes is between 250 and 900 kHz. Refer to Table 4-1 for more information.
4.1.3
PHASE REVERSAL
The MCP6G01/1R/1U/2/3/4 amplifier family is designed with CMOS input devices. It is designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-7 shows an input voltage exceeding both supplies with no resulting phase inversion.
(c) 2006 Microchip Technology Inc.
DS22004B-page 19
MCP6G01/1R/1U/2/3/4
4.1.4 INPUT VOLTAGE AND CURRENT LIMITS
current into the input pin (VIN) should be very small. A significant amount of current can flow out of the inputs when the common mode voltage (VCM) is below ground (VSS); see Figure 2-17. Applications that are high impedance may need to limit the useable voltage range. The ESD protection on the inputs can be depicted as shown in Figure 4-2. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass ESD events within the specified limits. VDD Bond Pad
4.1.5
RAIL-TO-RAIL OUTPUT
The maximum output voltage swing is the maximum swing possible under a particular amplifier load current. The amplifier load current is the sum of the external load current (IOUT) and the current through the ladder resistance (ILAD); see Figure 4-4.
EQUATION 4-2:
Input Stage to the rest of the amplifier Amplifier Load Current = I OUT + I LAD Where: ( V OUT - V SS ) I LAD = -------------------------------R LAD
VIN Bond Pad
VSS Bond Pad
FIGURE 4-2: Structures.
Simplified Analog Input ESD
VIN MCP6G0X
IOUT VOUT ILAD RLAD VSS
In order to prevent damage and/or improper operation of these amplifiers, the circuits they are in must limit the currents (and voltages) at the VIN pins (see Section "Absolute Maximum Ratings " at the beginning of Section 1.0 "Electrical Characteristics"). Figure 4-3 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN) from going too far below ground, and the resistor R1 limits the possible current drawn out of the input pin. Diode D1 prevents the input pin (VIN) from going too far above VDD. When implemented as shown, resistor R1 also limits the current through D1. VDD D1 V1 R1 VIN MCP6G0X VOUT
FIGURE 4-4:
Amplifier Load Current.
See Figure 2-20 for the typical output headroom (VDD - VOH or VOL - VSS) as a function of amplifier load current.The specification table states the output can reach within 10 mV of either supply rail when RL = 100 k.
4.2
Resistor Ladder
The resistor ladder shown in Figure 4-1 (RLAD = RF + RG) sets the gain. Placing the gain switches in series with the inverting input reduces the parasitic capacitance, distortion, and gain mismatch. RLAD is an additional load on the output of the SGA and causes additional current draw from the supplies. When CS is high, the SGA is shut down (low power). RLAD is still attached to the VOUT and VSS pins. Thus, these pins and the internal amplifier's inverting input are all connected through RLAD and the output is not high-Z (unlike the internal op amp). RLAD contributes to the output noise; see Figure 2-9.
R1
VSS - (minimum expected V1) 2 mA
FIGURE 4-3: Inputs.
Protecting the Analog
It is also possible to connect the diode to the left of the resistor R1. In this case, the current through the diode D1 needs to be limited by some other mechanism. The resistor then serves as in-rush current limiter; the DC
DS22004B-page 20
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MCP6G01/1R/1U/2/3/4
RLAD is intended to be driven at the VSS pin by a low impedance voltage source. The power supply driving the VSS pin should have an output impedance less than 0.1 to maintain reasonable gain accuracy.
TABLE 4-3:
Selected Gain +1 V/V
HARD WIRED GAIN SELECTION
Possible GSEL Drivers Open Circuit (Note 1) Low impedance source at VDD/2 Tied to GND (0V) Tied to VDD
4.3
MCP6G03 Chip Select (CS)
+10 V/V +50 V/V Note 1:
The MCP6G03 is a single amplifier with chip select (CS). When CS is high, the internal op amp is shut down and its output placed in a high-Z state. The resistive ladder is always connected between VSS and VOUT; even in shutdown. This means that the output resistance will be 350 k (typ.), with a path for output signals to appear at the input. The supply current at VSS includes the current through the load resistor and ladder resistors; it also includes current from the CS pin to VSS. When CS is low, the amplifier is enabled. If CS is left floating, the amplifier may not operate properly. Figure 1-2 and Figure 2-43 show how the output voltage and supply current response to a CS pulse.
The GSEL pin floats to mid-supply (VDD/2); a bypass capacitor may be needed.
4.5
Capacitive Load and Stability
4.4
Gain Select (GSEL)
The amplifier can be set to the gains +1 V/V, +10 V/V, and +50 V/V using one input pin (GSEL). At the same time, different compensation capacitors are selected to optimize the bandwidth vs. slew rate trade-off (see Table 4-1). Table 4-2 shows how to change the gain using a GPIO pin on a microcontroller and Table 4-3 shows how to hard wire the gain (i.e., using PCB wiring).
Large capacitive loads can cause stability problems and reduced bandwidth for the MCP6G01/1R/1U/2/3/4 family of SGAs (Figure 2-30 and Figure 2-34). As the load capacitance increases, there is a corresponding increase in frequency response peaking and step response overshoot and ringing. This happens because a large load capacitance decreases the internal amplifier's phase margin and bandwidth. When driving large capacitive loads with these SGAs (i.e., > 60 pF), a small series resistor at the output (RISO in Figure 4-5) improves the internal amplifier's stability by making the load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load.
TABLE 4-2:
Gain +1 V/V
MCU DRIVEN GAIN SELECTION
MCU Pin's State
RISO VIN MCP6G0X VOUT CL
Output PIC's VREF at VDD/2 Digital Output High-Z (Notes 1) Output VDD/2 PWM signal (Notes 2)
FIGURE 4-5: Capacitive Loads.
SGA Circuit for Large
+10 V/V +50 V/V Note 1:
Digital Output driven Low Digital Output driven High See Section 4.8.1 "Driving the Gain Select Pin with a Microcontroller GPIO Pin". See Section 4.8.2 "Driving the Gain Select Pin with a PWM Signal"
2:
Figure 4-6 gives recommended RISO values for different capacitive loads. After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot on the bench. Modify RISO's value until the response is reasonable at all gains.
(c) 2006 Microchip Technology Inc.
DS22004B-page 21
MCP6G01/1R/1U/2/3/4
4.6.3
1,000 Recommended RISO ( )
INPUT SOURCE IMPEDANCE
100
The sources driving the inputs of the SGAs need to have reasonably low source impedance at higher frequencies. Figure 4-7 shows how the external source resistance (RS), SGA package pin capacitance (CP1), and SGA package pin-to-pin capacitance (CP2) form a positive feedback voltage divider network. Feedback may cause frequency response peaking and step response overshoot and ringing.
For all gains
10 10p 10
100p 1n 10n 100 1,000 10,000 Load Capacitance (F)
100n 100,000
CP2
FIGURE 4-6:
Recommended RISO.
VS
RS MCP6G0X CP1 VOUT
4.6
Layout Considerations
Good PC board layout techniques will help achieve the performance shown in Section 1.0 "Electrical Characteristics" and Section 2.0 "Typical Performance Curves". It will also help minimize Electromagnetic Compatibility (EMC) issues. Because the MCP6G01/1R/1U/2/3/4 SGAs' frequency response reaches unity gain at 10 MHz when G = 50, it is important to use good PCB layout techniques. Any parasitic coupling at high frequency might cause undesired peaking. Filtering high frequency signals (i.e., fast edge rates) can help.
FIGURE 4-7:
Positive Feedback Path.
4.6.1
COMPONENT PLACEMENT
Separate different circuit functions: digital from analog, low speed from high speed, and low power from high power. This will reduce crosstalk. Keep sensitive traces short and straight. Separate them from interfering components and traces. This is especially important for high frequency (low rise time) signals.
Figure 2-10 shows the crosstalk (referred to input) that results when a hostile signal is connected to the other inputs (e.g., VINB through VIND), and the input of interest (e.g., VINA) has RS connected to GND. A gain of +50 was chosen for this plot because it demonstrates the worst-case behavior. Increasing RS increases the crosstalk as expected. At a source impedance of 10 M, there is noticeable change in behavior. Most designs should use a source resistance (RS) no larger than 10 M. Careful attention to layout parasitics and proper component selection will help minimize this effect. When a source impedance larger than 10 M must be used, place a capacitor in parallel to CP1 to reduce the positive feedback. This capacitor needs to be large enough to overcome gain (or crosstalk) peaking, yet small enough to allow a reasonable signal bandwidth.
4.6.2
SUPPLY BYPASS
Use a local bypass capacitor (0.01 F to 0.1 F) within 2 mm of the VDD pin for good, high frequency performance. It must connect directly to ground. Use a bulk bypass capacitor (i.e., 1.0 F to 10 F) within 100 mm of the VDD pin. It needs to connect to ground, and provides large, slow currents. This capacitor may be shared with other nearby analog parts. Ground plane is important, and power plane(s) can also be of great help. High frequency (e.g., multi-layer ceramic capacitors), surface mount components improve the supply's performance.
4.6.4
SIGNAL COUPLING
The input pins of the MCP6G01/1R/1U/2/3/4 family of SGAs are high impedance. This makes them especially susceptible to capacitively coupled noise. Using a ground plane helps reduce this problem. When noise is capacitively coupled, the ground plane provides additional shunt capacitance to ground. When noise is magnetically coupled, the ground plane reduces the mutual inductance between traces. Increasing the separation between traces makes a significant difference. Changing the direction of one of the traces can also reduce magnetic coupling. It may help to locate guard traces next to the victim trace. They should be on both sides of, and as close as possible to, the victim trace. Connect the guard traces to the ground plane at both ends. Also connect long guard traces to the ground plane in the middle.
(c) 2006 Microchip Technology Inc.
DS22004B-page 22
MCP6G01/1R/1U/2/3/4
4.7 Unused Amplifiers
4.8.2
An unused amplifier in a quad package (MCP6G04) should be configured as shown in Figure 4-8. This circuit prevents the output from toggling and causing crosstalk. Because the VIN pin looks like an open circuit, the GSEL voltage is automatically set at VDD/2, and the gain is 1 V/V. The output pin provides a buffered VDD/2 voltage and minimizes the supply current draw of the unused amplifier. 1/4 MCP6G04 VDD VDD VIN GSEL MCP6G0X VOUT PIC MCU PWM Output 10 k 10 k 4.7 nF 4.7 nF VIN GSEL MCP6G0X VOUT
DRIVING THE GAIN SELECT PIN WITH A PWM SIGNAL
The circuit in Figure 4-10 uses a PWM output on a PIC microcontroller (100 kHz clock rate) to drive the Gain Select input (GSEL). Setting the PWM duty cycle to 0%, 50% or 100% gives a GSEL voltage of 0V, VDD/2 or VDD, respectively (G = 10, 1 or 50). VDD
FIGURE 4-8:
Unused Amplifiers. FIGURE 4-10: Driving the GSEL Pin.
4.8
4.8.1
Typical Applications
DRIVING THE GAIN SELECT PIN WITH A MICROCONTROLLER GPIO PIN
The circuit in Figure 4-9 uses a microcontroller GPIO pin to drive the Gain Select input (GSEL). Setting the GPIO pin to logic low, high-Z or logic high gives a GSEL voltage of 0V, VDD/2 or VDD, respectively (G = 10, 1 or 50). VDD VDD MCU GPIO Pin
The PWM clock rate needs to be fast so it is easily filtered and does not interfere with the desired signal, and it needs to be slow enough for good accuracy and low crosstalk. This filter reduces the ripple at the GSEL pin to about 7 mVP-P at VDD = 5.0V. The 10% settling time is about 200 s; the filter limits how quickly the gain can be changed. Scale the resistors and/or capacitors for other clock rates, or for different ripple.
4.8.3
GAIN RANGING
VIN GSEL
MCP6G0X
VOUT
Figure 4-11 shows a circuit that measures the current IX. The circuit's performance benefits from changing the gain on the SGA. Just as a hand-held multimeter uses different measurement ranges to obtain the best results, this circuit makes it easy to set a high gain for small signals and a low gain for large signals. As a result, the required dynamic range at the SGA's output is less than at its input (by up to 34 dB).
FIGURE 4-9:
Driving the GSEL Pin.
IX RS
MCP6G0X
VOUT
The microcontroller's GPIO pin cannot produce a leakage current of more than 1 A for this circuit to function properly. In noisy environments, a capacitor may need to be added to the GPIO pin.
FIGURE 4-11: Wide Dynamic Range Current Measurement Circuit.
(c) 2006 Microchip Technology Inc.
DS22004B-page 23
MCP6G01/1R/1U/2/3/4
4.8.4 SHIFTED GAIN RANGE SGA 4.8.5 ADC DRIVER
Figure 4-12 shows a circuit using a MCP6271 at a gain of +10 in front of a MCP6G01. This shifts the overall gain range to +10 V/V to +500 V/V (from +1 V/V to +50 V/V). This family of SGAs is well suited for driving Analog-toDigital Converters (ADC). The gains (1, 10, and 50) effectively increase the ADC's input resolution by a factor of as large as 50 (i.e., by 5.6 bits). This works well for applications needing relative accuracy more than absolute accuracy (e.g., power monitoring); see Figure 4-14. Low-pass Filter VIN MCP6G01
VIN MCP6271 MCP6G01 VOUT
10.0 k 1.11 k
MCP3001 3 10-bit ADC
OUT
FIGURE 4-14: FIGURE 4-12: Range. SGA with Higher Gain
SGA as an ADC Driver.
It is also easy to shift the gain range to lower gains (see Figure 4-13). The MCP6001 acts as a unity gain buffer, and the resistive voltage divider shifts the gain range down to +0.1 V/V to +5.0 V/V (from +1 V/V to +50 V/V). VIN MCP6001 10.0 k VOUT MCP6G01 1.11 k
The low-pass filter in the block diagram reduces the integrated noise at the MCP6G01's output and serves as an anti-aliasing filter. This filter may be designed using Microchip's FilterLab(R) software, available at www.microchip.com.
FIGURE 4-13: Range.
SGA with Lower Gain
DS22004B-page 24
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SOT-23 (MCP6G01, MCP6G01R, MCP6G01U)
Device
Code CKNN CLNN CMNN
XXNN
MCP6G01 MCP6G01R MCP6G01U
CK25
Note: Applies to 5-Lead SOT-23
8-Lead SOIC (150 mil) (MCP6G01, MCP6G02, MCP6G03) XXXXXXXX XXXXYYWW NNN
Example:
MCP6G01E e3 SN^^0634 256
8-Lead MSOP (MCP6G01, MCP6G02, MCP6G03)
Example:
XXXXXX YWWNNN
6G01E 634256
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2006 Microchip Technology Inc.
DS22004B-page 25
MCP6G01/1R/1U/2/3/4
Package Marking Information (Continued)
14-Lead SOIC (150 mil) (MCP6S24) Example:
XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
MCP6G04 e3 E/SL^^ 0609256
14-Lead TSSOP (4.4mm) (MCP6S24)
Example:
XXXXXXXX YYWW NNN
6G04E/ST 0609 256
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
DS22004B-page 26
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
E E1
p B p1 D
n
1
c A A2
Units Dimension Limits Number of Pins Pitch Outside lead pitch (basic) Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n p p1 A A2 A1 E E1 D L f c B a b
L
A1
INCHES* MIN NOM 5 .038 .075 .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 .006 .017 5 5 .046 .043 .003 .110 .064 .116 .018 5 .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 0.35 0.90 0.90 0.00 2.60 1.50 2.80 0.35 MAX MIN
MILLIMETERS NOM 5 0.95 1.90 1.18 1.10 0.08 2.80 1.63 2.95 0.45 0 0.09 0 0 0.15 0.43 5 5 5 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 MAX
* Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Revised 09-12-05 Drawing No. C04-091
(c) 2006 Microchip Technology Inc.
DS22004B-page 27
MCP6G01/1R/1U/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1
NOTE 1 1 2 e b A2 c
A
A1 Units Dimension Limits N e A Thickness A2 A1 E Width E1 D L L1 c b
L1 MILLIMETERS NOM 8 0.65 BSC -- 0.85 -- 4.90 BSC 3.00 BSC 3.00 BSC 0.60 0.95 REF -- -- --
L
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Standoff Overall Width Molded Package Overall Length Foot Length Footprint Foot Angle Lead Thickness Lead Width
-- 0.75 0.00
1.10 0.95 0.15
0.40 0 0.08 0.22
0.80 8 0.23 0.40
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04-111, Sept. 8, 2006
DS22004B-page 28
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
E E1
p D 2 B n 1
h 45
c A
A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0
INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12
MAX
MIN
.069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15
MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057
(c) 2006 Microchip Technology Inc.
DS22004B-page 29
MCP6G01/1R/1U/2/3/4
14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
E E1
p
D
2 B n 1 h 45 c A A2
L A1
MAX Number of Pins Pitch Overall Height A .053 .069 1.75 Molded Package Thickness .052 .061 1.55 A2 Standoff A1 .004 .010 0.25 Overall Width E .228 .244 6.20 Molded Package Width E1 .150 .157 3.99 Overall Length D .337 .347 8.81 Chamfer Distance h .010 .020 0.51 Foot Length L .016 .050 1.27 Foot Angle 0 8 8 c Lead Thickness .008 .010 0.25 Lead Width B .014 .020 0.51 Mold Draft Angle Top 0 15 15 Mold Draft Angle Bottom 0 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 Revised 7-20-06
Units Dimension Limits n p
MIN
INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12
MAX
MIN
MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12
DS22004B-page 30
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
E E1 p
D
2 n B 1
A c
L Units Dimension Limits MIN n p A A2 A1 E E1 D L c B .039 .033 .002 .246 .169 .193 .020 0 .004 .007 INCHES NOM 14 .026 BSC .041 .035 .004 .251 .173 .197 .024 4 .006 .010 12 REF 12 REF
A1 MILLIMETERS* MAX MIN NOM 14 0.65 BSC .043 .037 .006 .256 .177 .201 .028 8 .008 .012 1.00 0.85 0.05 6.25 4.30 4.90 0.50 0 0.09 0.19 1.05 0.90 0.10 6.38 4.40 5.00 0.60 4 0.15 0.25 12 REF 12 REF
A2
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
1.10 0.95 0.15 6.50 4.50 5.10 0.70 8 0.20 0.30
* Controlling Parameter Notes: Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tole rance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-153 AB-1 Drawing No. C04-087
Revised: 08-17-05
(c) 2006 Microchip Technology Inc.
DS22004B-page 31
MCP6G01/1R/1U/2/3/4
NOTES:
DS22004B-page 32
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
APPENDIX A: REVISION HISTORY
Revision B (December 2006)
The following is the list of modifications: * Added SOT-23-5 package option for the single gain blocks MCP6G01, MCP6G01R, and MCP6G01U. * Added a discussion on VIN range vs. G.
Revision A (September 2006)
* Original Release of this Document.
(c) 2006 Microchip Technology Inc.
DS22004B-page 33
MCP6G01/1R/1U/2/3/4
NOTES:
DS22004B-page 34
(c) 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X Temperature Range /XX Package Examples:
a) b)
Single SGA Single SGA (Tape and Reel for MSOP and SOIC) Single SGA (Tape and Reel for SOT-23-5) Single SGA (Tape and Reel for SOT-23-5) Dual SGA Dual SGA (Tape and Reel for MSOP and SOIC) Single SGA Single SGA (Tape and Reel for MSOP and SOIC) Quad SGA Quad SGA (Tape and Reel for SOIC and TSSOP)
MCP6G01-E/MS:
Device:
MCP6G01: MCP6G01T: MCP6G01RT: MCP6G01UT: MCP6G02: MCP6G02T: MCP6G03: MCP6G03T: MCP6G04: MCP6G04T:
c)
d)
e)
Extended Temperature, 8LD MSOP. MCP6G01T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC. MCP6G01T-E/OT: Tape and Reel, Extended Temperature, 5LD SOT-23-5. MCP6G01RT-E/OT: Tape and Reel, Extended Temperature, 5LD SOT-23-5. MCP6G01UT-E/OT: Tape and Reel, Extended Temperature, 5LD SOT-23-5. MCP6G02-E/MS: Extended Temperature, 8LD MSOP. MCP6G02T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC. MCP6G03-E/MS: Extended Temperature, 8LD MSOP. MCP6G03T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC. MCP6G03-E/SN: Extended Temperature, 8LD SOIC. MCP6G04T-E/SL: Tape and Reel, Extended Temperature, 14LD SOIC. Tape and Reel, Extended Temperature, 14LD TSSOP. Extended Temperature, 14LD TSSOP.
a) b)
Temperature Range: Package:
E MS OT SN SL ST
= -40C to +125C
a)
= = = = = Plastic MSOP, 8-lead Plastic Small Outline Transistor (SOT-23-5), 5-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead (MCP6G04) Plastic TSSOP (4.4mm Body), 14-lead (MCP6G04)
b)
c) a)
b)
MCP6G04T-E/ST:
c)
MCP6G04-E/ST:
(c) 2006 Microchip Technology Inc.
DS22004B-page 35
MCP6G01/1R/1U/2/3/4
NOTES:
DS22004B-page 36
(c) 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2006 Microchip Technology Inc.
DS22004B-page 37
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
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EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
10/19/06
DS22004B-page 38
(c) 2006 Microchip Technology Inc.

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